Is your Boot Sequence Secure?
By leveraging Tortuga Logic's Unison platform, security checks can be performed on any silicon design that is running boot code. During boot, systems are especially prone to security vulnerabilities, as critical components of the system are being accessed and protections may not be active yet. Any RTL design with boot code that is undergoing functional verification with a simulation engine can now be tested for security vulnerabilities with the simple addition of Sentinel™ properties.
Leave no stone unturned
Tortuga Logic has collected a library of Sentinel™ properties that can be used in a push-button fashion. This library, in conjunction with custom Sentinel™ properties written through our Hardware Security Assessment services, ensures every security vulnerability of interest is checked. Nothing else is needed - perform security verification along with the functional verification you already perform today.
Uses your existing Simulation environment
Tortuga Logic's technology plugs into any standard simulation environment being utilized today. With the set of desired Sentinel™ properties provided by Tortuga Logic, a Security Model Design is generated, which is used to check the Sentinel™ properties and locate the exact location of security vulnerabilities. The Security Model Design is simply used for analysis and does not modify the original RTL.
- Dynamic (software driven) SoC Access Control Configuration
- Proper JTAG Disablement
- Software controlled key management
- Zeroization (tampering)
After simulation, Unison generates a robust set of results and debug information, including debug waveforms, vulnerability path information, and the location of each vulnerability.
To learn more, contact firstname.lastname@example.org