After many years of research, publications, and government funding, the Tortuga Logic team has created the most thorough approach to developing secure modern (CPU, chipset and SoC) semiconductor designs. This research has led to two important technologies that together allow for the creation and verification of secure chip designs:
1) Sentinel™ Security Language
2) Security Model Design
The application of these technologies can be applied over a “Hardware Security Development Lifecycle”* (HSDL) to a) describe security properties to be enforced and b) verify there are no vulnerabilities in the final design. This is shown below:
*Khattri et al.,”HSDL: A Security Development Lifecycle for Hardware Technologies”, 2012 IEEE International Symposium on Hardware-Oriented Security and Trust
Sentinel™ Security Language
The Sentinel™ Security Language can describe security properties at a high level of abstraction. By using Sentinel™ it is possible to express security requirements at a level that is independent of many implementation details of a design. This, in combination with augmenting the RTL to create the “Security Model Design”, optimizes the analysis of assets with security properties to enforce.
Security Model Design
The Security Model Design is an augmentation to the RTL, driven by Sentinel™ security properties that must be enforced. The powerful combination of the highly abstracted Security Properties and Security Model Design optimizes the ability to verify security properties throughout the entire silicon design flow.
Tortuga Logic was founded on the belief that current technologies and methods are not sufficient to ensure modern hardware security. The Sentinel™ Security Language coupled to a “Security Model Design” represent the core technologies that Tortuga Logic believes will be required to develop the secure silicon designs of the future.
To learn more, download our whitepaper here.